activity
20182025
most citedHey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification

10 citations · 15 across the 7 of their papers we have counts for

collaborators

7 papers

cs.AI2025★ 10 cited

Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification

Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Vaisakh Naduvodi Viswambharan +4

Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach…

cs.AI2025

Saarthi: The First AI Formal Verification Engineer

Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna +1

Recently, Devin has made a significant buzz in the Artificial Intelligence (AI) community as the world's first fully autonomous AI software engineer, capable of independently devel…

cs.AR2024

Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?

Bryan Olmos, Daniel Gerl, Aman Kumar +1

The design of Systems on Chips (SoCs) is becoming more and more complex due to technological advancements. Missed bugs can cause drastic failures in safety-critical environments le…

cs.AR2024

FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage

Deepak Narayan Gadde, Aman Kumar, Djones Lettnin +1

Ever-increasing design complexity of System-on-Chips (SoCs) led to significant verification challenges. Unlike software, bugs in hardware design are vigorous and eternal i.e., once…

cs.AI2024★ 5 cited

Efficient Stimuli Generation using Reinforcement Learning in Design Verification

Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar +3

The increasing design complexity of System-on-Chips (SoCs) has led to significant verification challenges, particularly in meeting coverage targets within a timely manner. At prese…

cs.LG2024

Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification

Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin +1

The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and runni…

cs.LO2018

A Scalable Approach for Hardware Semiformal Verification

Tomas Grimm, Djones Lettnin, Michael Hübner

The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation and FPGA prototyping. Howev…