6 papers
ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits
Jiajun Zou, Jiawei Liu, Ao Liu +8
As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and…
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie +3
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulatio…
Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction
Shan Shen, Yibin Zhang, Hector Rodriguez Rodriguez +1
Graph representation learning is a powerful method to extract features from graph-structured data, such as analog/mixed-signal (AMS) circuits. However, training deep learning model…
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits
Shan Shen, Shenglu Hua, Jiajun Zou +4
Graph representation learning on Analog-Mixed Signal (AMS) circuits is crucial for various downstream tasks, e.g., parasitic estimation. However, the scarcity of design data, the u…
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
Shan Shen, Zhiqiang Liu, Wenjian Yu
Designing the power delivery network (PDN) in very large-scale integrated (VLSI) circuits is increasingly important, especially for nowadays low-power integrated circuit (IC) desig…
Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection
Shan Shen, Hao Xu, Yongliang Zhou +2
In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshol…