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Cunxi Yu

2 papers hereh-index 14 citations4 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • sole author1
  • middle author1

Across the 2 of 2 papers where every author was matched, so the position is known.

fields
  • cs.AR1
  • cs.LG1
same name
  • Cunxi Yu — 18 papers, h 20
  • Cunxi Yu — 15 papers, h 8
  • Cunxi Yu — 11 papers, h 5
  • Cunxi Yu — 7 papers, h 6
  • Cunxi Yu — 4 papers, h 2
  • Cunxi Yu — 1 paper

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

collaborators
Showing cs.ARShow all

1 paper · 1 filter

cs.AR2025

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper

Cunxi Yu

LUT (Look-Up Table) mapping is a critical step in FPGA logic synthesis, where a logic network is transformed into a form that can be directly implemented using the FPGA's LUTs. An…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.