1 citations · 3 across the 11 of their papers we have counts for
11 papers
VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space
Yu-Tung Liu, Cunxi Yu
Large language models have shown promise for automated Verilog RTL generation, yet state-of-the-art multi-agent systems plateau at ~95% accuracy on standard benchmarks. We trace th…
Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
Cunxi Yu, Haoxing Ren
This paper introduces the first \emph{self-evolving} logic synthesis framework, which leverages Large Language Model (LLM) agents to autonomously improve the source code of \textsc…
TOPCELL: Topology Optimization of Standard Cell via LLMs
Zhan Song, Yu-Tung Liu, Chen Chen +6
Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optima…
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai +4
The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a proc…
ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers
Chen Chen, Daniela Kaufmann, Chenhui Deng +3
We present ReVEAL, a graph-learning-based method for reverse engineering of multiplier architectures to improve algebraic circuit verification techniques. Our framework leverages s…
e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
Jiaqi Yin, Zhan Song, Chen Chen +3
E-graphs have attracted growing interest in many fields, particularly in logic synthesis and formal verification. E-graph extraction is a challenging NP-hard combinatorial optimiza…
Revisit Choice Network for Synthesis and Technology Mapping
Chen Chen, Jiaqi Yin, Cunxi Yu
Choice network construction is a critical technique for alleviating structural bias issues in Boolean optimization, equivalence checking, and technology mapping. Previous works on…
HEC: Equivalence Verification Checking for Code Transformation via Equality Saturation
Jiaqi Yin, Zhan Song, Nicolas Bohm Agostini +2
In modern computing systems, compilation employs numerous optimization techniques to enhance code performance. Source-to-source code transformations, which include control flow and…
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Chen Chen, Guangyu HU, Cunxi Yu +2
In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equ…
BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
Jiaqi Yin, Zhan Song, Chen Chen +2
Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and add…
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
Chen Chen, Guangyu Hu, Dongsheng Zuo +3
Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing…