1 citations · 4 across the 11 of their papers we have counts for
11 papers
VeriPilot: An LLM-Powered Verilog Debugging Framework
Yihan Wang, Cheng Liu, Jiazheng Zhang +4
Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however…
ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing
Mingkai Chen, Cheng Liu, Shengwen Liang +3
Approximate nearest neighbor search(ANNS) is a critical kernel in modern applications such as LLM and recommendation systems.However,its efficiency is fundamentally limited by the…
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
Weixing Liu, Zizhen Liu, Jing Ye +4
As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasi…
GeoAgentBench: A Dynamic Execution Benchmark for Tool-Augmented Agents in Spatial Analysis
Bo Yu, Cheng Yang, Dongyang Hou +6
The integration of Large Language Models (LLMs) into Geographic Information Systems (GIS) marks a paradigm shift toward autonomous spatial analysis. However, evaluating these LLM-b…
Understanding and Mitigating Errors of LLM-Generated RTL Code
Jiazheng Zhang, Cheng Liu, Long Cheng +2
Despite limited success in large language model (LLM)-based register-transfer-level (RTL) code generation, the root causes of errors remain poorly understood. To address this, we c…
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA
Zesong Jiang, Qing Zhang, Cheng Liu +3
Open-source EDA tools are rapidly advancing, fostering collaboration, innovation, and knowledge sharing within the EDA community. However, the growing complexity of these tools, ch…
HLSPilot: LLM-based High-Level Synthesis
Chenwei Xiong, Cheng Liu, Huawei Li +1
Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the…
MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs
Junfeng Gong, Cheng Liu, Long Cheng +2
Mixed-precision neural network (MPNN) that utilizes just enough data width for the neural network processing is an effective approach to meet the stringent resources constraints in…
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
Xinmiao Zhang, Zheng Feng, Shengwen Liang +4
FPGA-based graph processing accelerators, enabling extensive customization, have demonstrated significant energy efficiency over general computing engines like CPUs and GPUs. Nonet…
SigDLA: A Deep Learning Accelerator Extension for Signal Processing
Fangfa Fu, Wenyu Zhang, Zesong Jiang +8
Deep learning and signal processing are closely correlated in many IoT scenarios such as anomaly detection to empower intelligence of things. Many IoT processors utilize digital si…
ApproxPilot: A GNN-based Accelerator Approximation Framework
Qing Zhang, Cheng Liu, Siting Liu +3
A typical optimization of customized accelerators for error-tolerant applications such as multimedia, recognition, and classification is to replace traditional arithmetic units lik…