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20242026
most citedHardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

3 citations · 5 across the 14 of their papers we have counts for

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cs.AR2025

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators

Yaman Umuroglu, Christoph Berganski, Felix Jentzsch +8

While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performan…