11 citations · 15 across the 11 of their papers we have counts for
6 papers · 1 filter
ReMaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating
Yunqi Shi, Xi Lin, Zhiang Wang +8
This work introduces the ReMaP method, which generates expert-quality macro placements through recursively prototyping and packing tree-based relocating. We first perf…
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
Ke Xue, Ruo-Tong Chen, Rong-Xi Tan +5
Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature pro…
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Zhexuan Xu, Kexin Zhou, Jie Wang +5
Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of…
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
Zhexuan Xu, Jie Wang, Siyuan Xu +3
Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However…
Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
Yunqi Shi, Chengrui Gao, Wanqi Ren +6
This work introduces Open3DBench, an open-source 3D-IC backend implementation benchmark built upon the OpenROAD-flow-scripts framework, enabling comprehensive evaluation of power,…
Timing-Driven Global Placement by Efficient Critical Path Extraction
Yunqi Shi, Siyuan Xu, Shixiong Kai +4
Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical metho…