1 citations · 1 across the 1 of their papers we have counts for
5 papers
ReMaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating
Yunqi Shi, Xi Lin, Zhiang Wang +8
This work introduces the ReMaP method, which generates expert-quality macro placements through recursively prototyping and packing tree-based relocating. We first perf…
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Zhexuan Xu, Kexin Zhou, Jie Wang +5
Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of…
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
Zhexuan Xu, Jie Wang, Siyuan Xu +3
Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However…
Timing-Driven Global Placement by Efficient Critical Path Extraction
Yunqi Shi, Siyuan Xu, Shixiong Kai +4
Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical metho…
Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer
Ke Xue, Ruo-Tong Chen, Xi Lin +4
In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. R…