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cs.PL2025
SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
Youwei Xiao, Yuyang Zou, Yun Liang
Hardware synthesis from high-level descriptions remains fundamentally limited by the sequential optimization of interdependent design decisions. Current methodologies, including st…
cs.PL2025
Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Youwei Xiao, Zizhang Luo, Weijie Peng +2
Hardware design faces a fundamental challenge: raising abstraction to improve productivity while maintaining control over low-level details like cycle accuracy. Traditional RTL des…