activity
20242026
most citedHiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

1 citations · 1 across the 5 of their papers we have counts for

collaborators

5 papers

cs.DC2026

SparseDitto: An Agentic Sparse Compilation Framework through Architecture-Aware Synthesis on GPUs

Shiyang Li, Guangyan Sun, Jinwei Tang +3

Sparse matrix computation performance on GPU depends on how representation and execution schedule match the input structure and target hardware. No single implementation consistent…

cs.AR2026

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing

Pengju Liu, Nuo Xu, Jinwei Tang +2

LLM-based agents are increasingly applied to the "last mile" of Electronic Design Automation (EDA): repairing residual sign-off Design Rule Check (DRC) violations and converging Po…

cs.CR2025

FHE-Agent: Automating CKKS Configuration for Practical Encrypted Inference via an LLM-Guided Agentic Framework

Nuo Xu, Zhaoting Gong, Ran Ran +3

Fully Homomorphic Encryption (FHE), particularly the CKKS scheme, is a promising enabler for privacy-preserving MLaaS, but its practical deployment faces a prohibitive barrier: it…

cs.AR2025

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging

Jinwei Tang, Jiayin Qin, Nuo Xu +5

As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and…

cs.LG2024★ 1 cited

HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

Jinwei Tang, Jiayin Qin, Kiran Thorat +5

With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL)…