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cs.LG2025
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
Kiran Thorat, Hongwu Peng, Yuebo Luo +8
Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gain…
cs.AR2025
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
Kiran Thorat, Jiahui Zhao, Yaotian Liu +5
Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the…
cs.LG2025
DR-CircuitGNN: Training Acceleration of Heterogeneous Circuit Graph Neural Network on GPUs
Yuebo Luo, Shiyang Li, Junran Tao +6
The increasing scale and complexity of integrated circuit design have led to increased challenges in Electronic Design Automation (EDA). Graph Neural Networks (GNNs) have emerged a…