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cs.CR2026★ 1 cited
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
Zeng Wang, Minghao Shao, Weimin Fu +6
The integration of large language models (LLMs) into electronic design automation (EDA) workflows has introduced powerful capabilities for RTL generation, verification, and design…
cs.AR2026
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
Prithwish Basu Roy, Zeng Wang, Anatolii Chuvashlov +4
Large Language Models (LLMs) have shown significant improvement in RTL code generation. Despite the advances, the generated code is often riddled with common vulnerabilities and we…