2 citations · 4 across the 7 of their papers we have counts for
4 papers · 1 filter
Revisiting Logic Encryption
Rupesh Raj Karn, Lakshmi Likhitha Mankali, Zeng Wang +5
Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection b…
LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
Akashdeep Saha, Zeng Wang, Prithwish Basu Roy +3
Despite rapid progress in logic locking (LL), reproducibility remains a challenge as codes are rarely made public. We present LockForge, a first-of-its-kind, multi-agent large lang…
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
Prithwish Basu Roy, Akashdeep Saha, Manaar Alam +4
Automated Verilog code synthesis poses significant challenges and typically demands expert oversight. Traditional high-level synthesis (HLS) methods often fail to scale for real-wo…
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Zeng Wang, Minghao Shao, Mohammed Nabeel +7
Large language models (LLMs) offer significant potential for coding, yet fine-tuning (FT) with curated data is essential for niche languages like Verilog. Using proprietary intelle…