3 papers
cs.AR2026
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng +1
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Perform…
cs.LG2025
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
Bin Sun, Jingyi Zhou, Jianan Mu +5
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-ne…
cs.AI2025
TRACE: Learning to Compute on Circuit Graphs
Ziyang Zheng, Jiaying Zhu, Jingyi Zhou +1
Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning. Yet, the dominant paradigm is ar…