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cs.AR2024
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
Karthik Maddala, Bhabesh Mali, Chandan Karfa
Writing SystemVerilog Assertions (SVA) is an important but complex step in verifying Register Transfer Level (RTL) designs. Conventionally, experts need to understand the design sp…
cs.SE2024
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
Bhabesh Mali, Karthik Maddala, Vatsal Gupta +3
System Verilog Assertion (SVA) formulation -- a critical yet complex task is a prerequisite in the Assertion Based Verification (ABV) process. Traditionally, SVA formulation involv…