4 papers
LLM Assisted Verification Assertion Generation: Challenges and Future Directions
Bhabesh Mali, Chandan Karfa
Assertion-based Verification (ABV) plays a critical role in the Design Verification (DV) process. However, ABV requires substantial manual effort in generating assertion from speci…
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
Shashwat Shankar, Subhranshu Pandey, Innocent Dengkhw Mochahari +4
Large Language Model(LLM) inference demands massive compute and energy, making domain-specific tasks expensive and unsustainable. As foundation models keep scaling, we ask: Is bigg…
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
Adarsh Gupta, Bhabesh Mali, Chandan Karfa
Recent advancements in the field of reasoning using Large Language Models (LLMs) have created new possibilities for more complex and automatic Hardware Assertion Generation techniq…
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
Karthik Maddala, Bhabesh Mali, Chandan Karfa
Writing SystemVerilog Assertions (SVA) is an important but complex step in verifying Register Transfer Level (RTL) designs. Conventionally, experts need to understand the design sp…