4 papers · 1 filter
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai +4
The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a proc…
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho +2
Debugging formal verification (FV) failures represents one of the most time-consuming bottlenecks in modern hardware design workflows. When properties fail, engineers must manually…
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
Chia-Tung Ho, Jing Gong, Yunsheng Bai +3
Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing perfor…
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Chenhui Deng, Yunsheng Bai, Haoxing Ren
Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo ha…