6 papers
Learning to Debug: LLM-Organized Knowledge Trees for Solving RTL Assertion Failures
Yunsheng Bai, Haoxing Ren
Debugging is the dominant cost in modern hardware verification, where assertion failures are among the most frequent and expensive to resolve. While Large Language Models (LLMs) sh…
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho +2
Debugging formal verification (FV) failures represents one of the most time-consuming bottlenecks in modern hardware design workflows. When properties fail, engineers must manually…
Polymath: A Self-Optimizing Agent with Dynamic Hierarchical Workflow
Chia-Tung Ho, Jing Gong, Xufeng Yao +3
Large language models (LLMs) excel at solving complex tasks by executing agentic workflows composed of detailed instructions and structured operations. Yet, building general-purpos…
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
Chia-Tung Ho, Jing Gong, Yunsheng Bai +3
Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing perfor…
AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL
Yunsheng Bai, Ghaith Bany Hamad, Syed Suhaib +1
Generating SystemVerilog Assertions (SVAs) from natural language specifications remains a major challenge in formal verification (FV) due to the inherent ambiguity and incompletene…
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
Chenhui Deng, Yunsheng Bai, Haoxing Ren
Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo ha…