1 citations · 3 across the 9 of their papers we have counts for
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E-Layout: Layout-Stage Logic Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation
Wenji Fang, Rongjian Liang, Yi-Chen Lu +7
Achieving high sign-off performance in advanced ICs increasingly depends on layout-stage optimization under realistic physical conditions. While recent efforts have moved toward sy…
Revisit Choice Network for Synthesis and Technology Mapping
Chen Chen, Jiaqi Yin, Cunxi Yu
Choice network construction is a critical technique for alleviating structural bias issues in Boolean optimization, equivalence checking, and technology mapping. Previous works on…
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Chen Chen, Guangyu HU, Cunxi Yu +2
In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equ…
BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
Jiaqi Yin, Zhan Song, Chen Chen +2
Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and add…
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
Chen Chen, Guangyu Hu, Dongsheng Zuo +3
Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing…