1 citations · 3 across the 9 of their papers we have counts for
11 papers
E-Layout: Layout-Stage Logic Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation
Wenji Fang, Rongjian Liang, Yi-Chen Lu +7
Achieving high sign-off performance in advanced ICs increasingly depends on layout-stage optimization under realistic physical conditions. While recent efforts have moved toward sy…
CircuitProver: Agentic Lean 4 Theorem Proving with Reusable Circuit Proof Library for Hardware Verification
Ziyi Yang, Wenji Fang, Chen Chen +2
Modern integrated circuits (ICs) are becoming increasingly complex, making functional verification a major bottleneck. The dominant hardware formal verification methodology, model…
TOPCELL: Topology Optimization of Standard Cell via LLMs
Zhan Song, Yu-Tung Liu, Chen Chen +6
Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optima…
Avoiding Big Integers: Parallel Multimodular Algebraic Verification of Arithmetic Circuits
Clemens Hofstadler, Daniela Kaufmann, Chen Chen
Word-level verification of arithmetic circuits with large operands typically relies on arbitrary-precision arithmetic, which can lead to significant computational overhead as word…
ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers
Chen Chen, Daniela Kaufmann, Chenhui Deng +3
We present ReVEAL, a graph-learning-based method for reverse engineering of multiplier architectures to improve algebraic circuit verification techniques. Our framework leverages s…
e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
Jiaqi Yin, Zhan Song, Chen Chen +3
E-graphs have attracted growing interest in many fields, particularly in logic synthesis and formal verification. E-graph extraction is a challenging NP-hard combinatorial optimiza…
Revisit Choice Network for Synthesis and Technology Mapping
Chen Chen, Jiaqi Yin, Cunxi Yu
Choice network construction is a critical technique for alleviating structural bias issues in Boolean optimization, equivalence checking, and technology mapping. Previous works on…
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
Chen Chen, Guangyu HU, Cunxi Yu +2
In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equ…
BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
Jiaqi Yin, Zhan Song, Chen Chen +2
Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and add…
The Phantom of PCIe: Constraining Generative Artificial Intelligences for Practical Peripherals Trace Synthesizing
Zhibai Huang, Chen Chen, James Yen +9
Peripheral Component Interconnect Express (PCIe) is the de facto interconnect standard for high-speed peripherals and CPUs. The development of PCIe devices for emerging application…
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
Chen Chen, Guangyu Hu, Dongsheng Zuo +3
Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing…