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cs.AI2025
Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities
Jiaying Zhu, Ziyang Zheng, Zhengyuan Shi +2
Circuit Satisfiability (CSAT) plays a pivotal role in Electronic Design Automation. The standard workflow for solving CSAT problems converts circuits into Conjunctive Normal Form (…
cs.AI2025
Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism
Ziyang Zheng, Kezhi Li, Zhengyuan Shi +1
Subgraph matching in logic circuits is foundational for numerous Electronic Design Automation (EDA) applications, including datapath optimization, arithmetic verification, and hard…