1 citations · 2 across the 6 of their papers we have counts for
5 papers · 1 filter
Catscan: Visualizing Pipelines of CPU Performance Simulation
Aaron Lindsay, Nicholas Kelly, Scott Witscher +1
Processor pipeline visualization tools are routine inside industry CPU teams, but few of them are described or released publicly. As a result, students, researchers, and other prac…
PANEM: A Heuristic Latency Model
Lucas Crowthers, Mahesh Madhav
Accurate pre-silicon memory modeling is essential for achieving meaningful representation of workloads on cloud-class many-core processors. Existing options force a poor tradeoff b…
Performance Verification of the AmpereOne CPU Core
Doa'a Al-Otoom, Nicholas Kelly, Aaron Lindsay +16
As process technology scaling slows, microarchitectural innovation has become the primary driver of performance gains, making pre-silicon Performance Verification (PV) more critica…
Optimized Memory Tagging on AmpereOne Processors
Shivnandan Kaushik, Mahesh Madhav, Nagi Aboulenein +14
Memory-safety escapes continue to form the launching pad for a wide range of security attacks, especially for the substantial base of deployed software that is coded in pointer-bas…
Memory Access Vectors: Improving Sampling Fidelity for CPU Performance Simulations
Sriyash Caculo, Mahesh Madhav, Jeff Baxter
Accurate performance projection of large-scale benchmarks is essential for CPU architects to evaluate and optimize future processor designs. SimPoint sampling, which uses Basic Blo…