1 citations · 2 across the 6 of their papers we have counts for
9 papers
Catscan: Visualizing Pipelines of CPU Performance Simulation
Aaron Lindsay, Nicholas Kelly, Scott Witscher +1
Processor pipeline visualization tools are routine inside industry CPU teams, but few of them are described or released publicly. As a result, students, researchers, and other prac…
Rolling Round-Robin Rate: Standard Heterogeneous Throughput for SPEC CPU
Mahesh Madhav, Christoph Müllner, Jiangning Liu +2
SPEC CPU has long provided a common foundation for comparing processor, compiler, memory-system, and platform performance. Its multi-copy SPECrate mode measures homogeneous through…
PANEM: A Heuristic Latency Model
Lucas Crowthers, Mahesh Madhav
Accurate pre-silicon memory modeling is essential for achieving meaningful representation of workloads on cloud-class many-core processors. Existing options force a poor tradeoff b…
Adaptation Fidelity of SPEC CPU2026
Doa'a Al-Otoom, Mahesh Madhav
Standardized benchmarks are often criticized for not being "real workloads," but this critique is rarely backed by data. This paper provides the first systematic, quantitative anal…
Performance Verification of the AmpereOne CPU Core
Doa'a Al-Otoom, Nicholas Kelly, Aaron Lindsay +16
As process technology scaling slows, microarchitectural innovation has become the primary driver of performance gains, making pre-silicon Performance Verification (PV) more critica…
SPEC CPU: The Next Generation
Mahesh Madhav, Allen Lee, Andres Mejia +31
The march toward developing relevant and robust CPU benchmarks continues with the introduction of SPEC CPU 2026, the next generation suite for measuring processor performance. This…
ARM MTE Performance in Practice (Extended Version)
Taehyun Noh, Yingchen Wang, Tal Garfinkel +4
We present the first comprehensive analysis of ARM MTE hardware performance on four different microarchitectures: ARM Big (A7x), Little (A5x), and Performance (Cortex-X) cores on t…
Optimized Memory Tagging on AmpereOne Processors
Shivnandan Kaushik, Mahesh Madhav, Nagi Aboulenein +14
Memory-safety escapes continue to form the launching pad for a wide range of security attacks, especially for the substantial base of deployed software that is coded in pointer-bas…
Memory Access Vectors: Improving Sampling Fidelity for CPU Performance Simulations
Sriyash Caculo, Mahesh Madhav, Jeff Baxter
Accurate performance projection of large-scale benchmarks is essential for CPU architects to evaluate and optimize future processor designs. SimPoint sampling, which uses Basic Blo…