7 citations · 8 across the 7 of their papers we have counts for
8 papers
Verification of Compiler-to-Accelerator Mappings for Machine Learning Accelerators
Akash Gaonkar, Mike He, Yi Li +8
To meet the performance needs of modern machine learning (ML) applications, ML compiler frameworks support compiler-to-accelerator mappings that offload parts of application code t…
Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing
Yu-Wei Fan, Yuheng Yang, Christine Guo +4
Register-Transfer Level (RTL) simulation is widely used to test hardware before it is fabricated. To allow testing for security related information flow properties, such as confide…
Theory-Level Autoformalization: From Isolated Statements to Unified Formal Knowledge Bases
Marcus J. Min, Mike He, Zhaoyu Li +5
Autoformalization translates informal natural language into formal, machine-verifiable languages. While most work focuses on individual statements, real formalization efforts are i…
SecIC3: Customizing IC3 for Hardware Security Verification
Qinhan Tan, Akash Gaonkar, Yu-Wei Fan +2
Recent years have seen significant advances in using formal verification to check hardware security properties. Of particular practical interest are checking confidentiality and in…
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
Yu-An Shih, Annie Lin, Aarti Gupta +1
Formal specifications of on-chip communication protocols are crucial for system-on-chip (SoC) design and verification. However, manually constructing these formal specifications fr…
RTL Verification for Secure Speculation Using Contract Shadow Logic
Qinhan Tan, Yuheng Yang, Thomas Bourgeat +2
Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from…
Combined Scheduling, Memory Allocation and Tensor Replacement for Minimizing Off-Chip Data Accesses of DNN Accelerators
Yi Li, Aarti Gupta, Sharad Malik
Specialized hardware accelerators have been extensively used for Deep Neural Networks (DNNs) to provide power/performance benefits. These accelerators contain specialized hardware…
Security Verification of Low-Trust Architectures
Qinhan Tan, Yonathan Fisseha, Shibo Chen +4
Low-trust architectures work on, from the viewpoint of software, always-encrypted data, and significantly reduce the amount of hardware trust to a small software-free enclave compo…