12 papers
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Haoyi Zhang, Weijian Fan, Xiaohan Gao +3
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Haoyi Zhang, Kairong Guo, Bojie Zhang +2
Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…
RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
Zizhuo Fu, Yifan Zhou, Zhaoxin Lu +4
Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained l…
LaMoSys3.5D: Enabling 3.5D-IC-Based Large Language Model Inference Serving Systems via Hardware/Software Co-Design
Qipan Wang, Zhe Zhang, Shuangchen Li +5
The success of large language models LLMs amplifies the need for highthroughput energyefficient inference at scale. 3DDRAMbased accelerators provide high memory bandwidth and there…
ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC
Qipan Wang, Tianxiang Zhu, Tianyu Jia +3
Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integra…
HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support
Zizheng Guo, Haichuan Liu, Xizhe Shi +5
We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile a…