1 citations · 1 across the 4 of their papers we have counts for
5 papers
Si/SiGe multi-channel superlattice structure epitaxial growth with segmented temperature control for Next-Generation Logic Devices
Wenlong Yao, Zhigang Li, Guobin Bai +5
Stacking multiple SiSiGe channels in advanced logic devices faces severe thermal budget accumulation, which degrades interfaces via Ge-Si interdiffusion and strain relaxation.This…
Unveiling Retention Loss Mechanism in FeFETs with Gate-side Interlayer by Decoupling Trapped Charges and Ferroelectric Polarization
Runhao Han, Tao Hu, Jia Yang +10
We propose a direct experimental extraction technique for trapped charges and quantitative energy band diagrams in the FeFETs with metal-insulator-ferroelectric-insulator-semicondu…
Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
Tao Hu, Xianzhou Shao, Mingkai Bai +13
We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS…
Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
Tao Hu, Xianzhou Shao, Mingkai Bai +13
We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases wit…
Enlargement of Memory Window of Si Channel FeFET by Inserting Al2O3 Interlayer on Ferroelectric Hf0.5Zr0.5O2
Tao Hu, Xiaoqing Sun, Mingkai Bai +12
In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf0.5Zr0.5O2 by gate-side dielectric interlayer engineering. By inserting a…