1 citations · 1 across the 8 of their papers we have counts for
9 papers
CITADEL: CWE-Guided Insertion of Hardware Trojans via Analysis of DFG-Enabled LLMs
Jayanth Thangellamudi, Raghul Saravanan, Sudipta Paria +2
The increasing sophistication of Hardware Trojans (HTs) and system-level vulnerabilities poses significant risks to modern integrated circuits. However, constructing realistic HT s…
SoK: ARCUS: On the Efficiency and Efficacy of Hardware Fuzzing
Alenkruth Krishnan Murali, Raghul Saravanan, Sai Manoj P D +1
This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarch…
Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights
Sudipta Paria, Aritra Dasgupta, Raghul Saravanan +3
Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verifica…
An Automated Framework for Generating Stealthy Cell-Embedded Hardware Trojans
Raghul Saravanan, Sudipta Paria, Sai Manoj P D +1
Hardware Trojans (HTs) pose significant threats across the Integrated Circuit (IC) design lifecycle because they can be inserted by untrusted entities at different stages under the…
Logic Solver Guided Directed Fuzzing for Hardware Designs
Raghul Saravanan, Sai Manoj P D
The ever-increasing complexity of design specifications for processors and intellectual property (IP) presents a formidable challenge for early bug detection in the modern IC desig…
Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +2
Hardware Fuzzing emerged as one of the crucial techniques for finding security flaws in modern hardware designs by testing a wide range of input scenarios. One of the main challeng…
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +3
In the evolving landscape of integrated circuit (IC) design, the increasing complexity of modern processors and intellectual property (IP) cores has introduced new challenges in en…
Accelerating Hardware Verification with Graph Models
Raghul Saravanan, Sreenitha Kasarapu, Sai Manoj Pudukotai Dinakarrao
The increasing complexity of modern processor and IP designs presents significant challenges in identifying and mitigating hardware flaws early in the IC design cycle. Traditional…
The Emergence of Hardware Fuzzing: A Critical Review of its Significance
Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao
In recent years, there has been a notable surge in attention towards hardware security, driven by the increasing complexity and integration of processors, SoCs, and third-party IPs…