6 papers · 1 filter
Rethinking Unified Memory for NPU-PIM Systems: Dual-View Memory for Dynamic Inference of LLM
Shixin Zhao, Lian Liu, Tianhua Han +3
Heterogeneous architectures that combine neural processing unit (NPU) and processing-in-memory (PIM) are increasingly adopted to accelerate LLM inference. Prior work focuses on bui…
RTLCurator: Label-Efficient Data Curation for RTL Generation
Siyang Cai, Cangyuan Li, Wenjing Chang +4
Training large language models (LLMs) to write register-transfer level (RTL) requires large corpora of paired specifications and code, and such data is scarce enough that most publ…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference
Yiqi Liu, Yudong Pan, Mengdi Wang +5
Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based…
PAM: Processing Across Memory Hierarchy for Efficient KV-centric LLM Serving System
Lian Liu, Shixin Zhao, Yutian Zhou +4
The widespread adoption of Large Language Models (LLMs) has exponentially increased the demand for efficient serving systems. With growing requests and context lengths, key-value (…
Large Processor Chip Model
Kaiyan Chang, Mingzhi Chen, Yunji Chen +40
Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and R…