12 papers
Learning to Compute Is Not Learning to Retain or Reuse in Looped Transformers
Peilong Zhou, Hongtao Zhang, Yulong Huang +3
Looped transformers compute by applying one block repeatedly, so they can run for more loops than they were trained with. Recurrent reasoners are known to overthink: iterating past…
Rethinking Unified Memory for NPU-PIM Systems: Dual-View Memory for Dynamic Inference of LLM
Shixin Zhao, Lian Liu, Tianhua Han +3
Heterogeneous architectures that combine neural processing unit (NPU) and processing-in-memory (PIM) are increasingly adopted to accelerate LLM inference. Prior work focuses on bui…
RTLCurator: Label-Efficient Data Curation for RTL Generation
Siyang Cai, Cangyuan Li, Wenjing Chang +4
Training large language models (LLMs) to write register-transfer level (RTL) requires large corpora of paired specifications and code, and such data is scarce enough that most publ…
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heteroge…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs. Recent systems improve further through…
Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference
Yiqi Liu, Yudong Pan, Mengdi Wang +5
Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based…
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
Siyang Cai, Cangyuan Li, Haoyu Gao +3
Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly…
PAM: Processing Across Memory Hierarchy for Efficient KV-centric LLM Serving System
Lian Liu, Shixin Zhao, Yutian Zhou +4
The widespread adoption of Large Language Models (LLMs) has exponentially increased the demand for efficient serving systems. With growing requests and context lengths, key-value (…
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
Zhirong Chen, Kaiyan Chang, Zhuolin Li +8
Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…
Large Processor Chip Model
Kaiyan Chang, Mingzhi Chen, Yunji Chen +40
Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and R…
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework
Kun Wang, Kaiyan Chang, Mengdi Wang +4
Recent advances of large language models in the field of Verilog generation have raised several ethical and security concerns, such as code copyright protection and dissemination o…