59 citations · 87 across the 8 of their papers we have counts for
12 papers
Euclid Bypass end-to-end simulations for spectroscopic galaxy clustering performance assessment
Euclid Collaboration, B. R. Granett, S. de la Torre +321
We present a simulation framework for Euclid galaxy clustering measurements that reproduces the essential behaviour of the spectroscopic reduction chain, bypassing the computation…
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heteroge…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs. Recent systems improve further through…
A System Architecture for Low Latency Multiprogramming Quantum Computing
Yilun Zhao, Yu Chen, Kaiyan Chang +4
As quantum systems scale, multiprogramming quantum computing (MPQC) provides a practical way to improve device utilization and throughput. However, because quantum executables are…
LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow
Kaiyan Chang, Wenlong Zhu, Shengwen Liang +2
Accurate and fast performance prediction for dataflow-based accelerators is vital for efficient hardware design and design space exploration, yet existing methods struggle to gener…
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
Zhirong Chen, Kaiyan Chang, Zhuolin Li +8
Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…
Large Processor Chip Model
Kaiyan Chang, Mingzhi Chen, Yunji Chen +40
Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and R…
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework
Kun Wang, Kaiyan Chang, Mengdi Wang +4
Recent advances of large language models in the field of Verilog generation have raised several ethical and security concerns, such as code copyright protection and dissemination o…
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Kaiyan Chang, Zhirong Chen, Yunhao Zhou +9
Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large la…
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Kaiyan Chang, Kun Wang, Nan Yang +16
Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers…
ChipGPT: How far are we from natural language hardware design
Kaiyan Chang, Ying Wang, Haimeng Ren +5
As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficie…