activity
20242026
most citedReducedLUT: Table Decomposition with "Don't Care" Conditions

8 citations · 9 across the 12 of their papers we have counts for

collaborators
Showing cs.ARShow all

7 papers · 1 filter

cs.AR2026

CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs

Oliver Cassidy, Marta Andronic, George A. Constantinides

Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to re…

cs.AR2025

Banked Memories for Soft SIMT Processors

Martin Langhammer, George A. Constantinides

Recent advances in soft GPGPU architectures have shown that a small (<10K LUT), high performance (770 MHz) processor is possible in modern FPGAs. In this paper we architect and eva…

cs.AR2025

AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks

Pedro Gimenes, Yiren Zhao, George Constantinides

Graph Neural Networks (GNNs) have recently gained attention due to their performance on non-Euclidean data. The use of custom hardware architectures proves particularly beneficial…

cs.AR2024★ 8 cited

ReducedLUT: Table Decomposition with "Don't Care" Conditions

Oliver Cassidy, Marta Andronic, Samuel Coward +1

Lookup tables (LUTs) are frequently used to efficiently store arrays of precomputed values for complex mathematical computations. When used in the context of neural networks, these…

cs.AR2024

ROVER: RTL Optimization via Verified E-Graph Rewriting

Samuel Coward, Theo Drane, George A. Constantinides

Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Ou…

cs.AR2024

Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap

Martin Langhammer, George A. Constantinides

eGPU, a recently-reported soft GPGPU for FPGAs, has demonstrated very high clock frequencies (more than 750 MHz) and small footprint. This means that for the first time, commercial…

cs.AR2024★ 1 cited

Combining Power and Arithmetic Optimization via Datapath Rewriting

Samuel Coward, Theo Drane, Emiliano Morini +1

Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are theref…