8 citations · 9 across the 12 of their papers we have counts for
12 papers
When Does Disaggregation Pay? Simulating Prefill--Decode--Attention--FFN Specialization for Agentic LLM Inference
Przemyslaw Forys, Haoran Wu, Can Xiao +8
Agentic inference now dominates the LLM inference landscape, requiring LLMs to actively engage in multi-turn interactions with tool-calling capabilities. This introduces a more com…
CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs
Oliver Cassidy, Marta Andronic, George A. Constantinides
Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to re…
Direction-Preserving Number Representations
Bardia Zadeh, George A. Constantinides
Low-precision number formats are widely used in modern machine learning systems due to their efficiency. Accurate direction representation is key to the accuracy of vector operatio…
Training with Fewer Bits: Unlocking Edge LLMs Training with Stochastic Rounding
Taowen Liu, Marta Andronic, Deniz Gündüz +1
LLM training is resource-intensive. Quantized training improves computational and memory efficiency but introduces quantization noise, which can hinder convergence and degrade mode…
NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference
Marta Andronic, George A. Constantinides
Efficient neural networks (NNs) leveraging lookup tables (LUTs) have demonstrated significant potential for emerging AI applications, particularly when deployed on field-programmab…
Banked Memories for Soft SIMT Processors
Martin Langhammer, George A. Constantinides
Recent advances in soft GPGPU architectures have shown that a small (<10K LUT), high performance (770 MHz) processor is possible in modern FPGAs. In this paper we architect and eva…
AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks
Pedro Gimenes, Yiren Zhao, George Constantinides
Graph Neural Networks (GNNs) have recently gained attention due to their performance on non-Euclidean data. The use of custom hardware architectures proves particularly beneficial…
PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning
Marta Andronic, Jiawen Li, George A. Constantinides
Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has…
ReducedLUT: Table Decomposition with "Don't Care" Conditions
Oliver Cassidy, Marta Andronic, Samuel Coward +1
Lookup tables (LUTs) are frequently used to efficiently store arrays of precomputed values for complex mathematical computations. When used in the context of neural networks, these…
ROVER: RTL Optimization via Verified E-Graph Rewriting
Samuel Coward, Theo Drane, George A. Constantinides
Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Ou…
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap
Martin Langhammer, George A. Constantinides
eGPU, a recently-reported soft GPGPU for FPGAs, has demonstrated very high clock frequencies (more than 750 MHz) and small footprint. This means that for the first time, commercial…
Combining Power and Arithmetic Optimization via Datapath Rewriting
Samuel Coward, Theo Drane, Emiliano Morini +1
Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are theref…