14 citations · 26 across the 4 of their papers we have counts for
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cs.AR2025
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2
Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…
cs.AR2025★ 14 cited
Stream-HLS: Towards Automatic Dataflow Acceleration
Suhail Basalama, Jason Cong
High-level synthesis (HLS) has enabled the rapid development of custom hardware circuits for many software applications. However, developing high-performance hardware circuits usin…
cs.AR2022★ 12 cited
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
Linghao Song, Licheng Guo, Suhail Basalama +3
The continued growth in the processing power of FPGAs coupled with high bandwidth memories (HBM), makes systems like the Xilinx U280 credible platforms for linear solvers which oft…