14 citations · 26 across the 4 of their papers we have counts for
4 papers
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2
Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…
Stream-HLS: Towards Automatic Dataflow Acceleration
Suhail Basalama, Jason Cong
High-level synthesis (HLS) has enabled the rapid development of custom hardware circuits for many software applications. However, developing high-performance hardware circuits usin…
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
Neha Prakriya, Yuze Chi, Suhail Basalama +2
Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverag…
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
Linghao Song, Licheng Guo, Suhail Basalama +3
The continued growth in the processing power of FPGAs coupled with high bandwidth memories (HBM), makes systems like the Xilinx U280 credible platforms for linear solvers which oft…