2 citations · 2 across the 8 of their papers we have counts for
5 papers · 1 filter
RailX: A Flexible, Scalable, and Low-Cost Network Architecture for Hyper-Scale LLM Training Systems
Yinxiao Feng, Tiancheng Chen, Yuchen Wei +5
Increasingly large AI workloads are calling for hyper-scale infrastructure; however, traditional interconnection network architecture is neither scalable nor cost-effective enough.…
SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
Jingwei Cai, Xuan Wang, Mingyu Gao +5
Modern Deep Neural Network (DNN) accelerators are equipped with increasingly larger on-chip buffers to provide more opportunities to alleviate the increasingly severe DRAM bandwidt…
Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration
Yinxiao Feng, Kaisheng Ma
Existing high-performance computing (HPC) interconnection architectures are based on high-radix switches, which limits the injection/local performance and introduces latency/energy…
Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization
Zhanhong Tan, Zijian Zhu, Kaisheng Ma
Memory is a critical design consideration in current data-intensive DNN accelerators, as it profoundly determines energy consumption, bandwidth requirements, and area costs. As DNN…
Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
Jingwei Cai, Zuotong Wu, Sen Peng +5
Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computatio…