activity
20242026
most citedVRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

1 citations · 1 across the 4 of their papers we have counts for

collaborators

5 papers

cs.AR2026

VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation

Zhuorui Zhao, Bing Li, Yu Li +2

Large language models (LLMs) have demonstrated promising capabilities in generating Verilog code from natural language specifications. However, human-written specifications often c…

cs.AR2025

VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning

Zhuorui Zhao, Bing Li, Grace Li Zhang +1

Large Language Models (LLMs) have shown impressive potential in generating Verilog codes, but ensuring functional correctness remains a challenge. Existing approaches often rely on…

eess.SY2025

Large Language Models (LLMs) for Electronic Design Automation (EDA)

Kangwei Xu, Denis Schwachhofer, Jason Blocklove +10

With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involve…

cs.AR20251 cited

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin +3

Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes,…

eess.SY2024

LLM-Aided Efficient Hardware Design Automation

Kangwei Xu, Ruidi Qiu, Zhuorui Zhao +3

With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more effort in tasks such as circuit design, verification, and physical implementa…