2 papers
cond-mat.mes-hall2025
Overlay-aware Variation Study of Flip FET and Benchmark with CFET
Wanyue Peng, Haoran Lu, Jingru Jiang +5
In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside process…
physics.app-ph2025
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals
Haoran Lu, Xun Jiang, Yanbang Chu +7
As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering cons…