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20242026
most citedSimulations and Performance Studies of a MAPS in 65 nm CMOS Imaging Technology

4 citations · 4 across the 6 of their papers we have counts for

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physics.ins-det2026

Review of prototypes developed in a 65 nm CMOS imaging technology in view of vertexing applications at a future lepton collider

Finn King, Matthew Lewis Franks, Yajun He +21

The OCTOPUS project addresses the development and characterization of monolithic active pixel sensors in the TPSCo 65 nm ISC technology in view of vertexing applications at a futur…

physics.ins-det2025

Characterization of the H2M Monolithic CMOS Sensor

Rafael Ballabriga, Eric Buschmann, Michael Campbell +29

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addre…

physics.ins-det2025

Impact of the circuit layout on the charge collection in a monolithic pixel sensor

Corentin Lemoine, Rafael Ballabriga, Eric Buschmann +28

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors fo…

physics.ins-det2025

Transient studies using a TCAD and Allpix Squared combination approach

Manuel A. Del Rio Viera, Eric Buschmann, Ankur Chauhan +22

The goal of the TANGERINE project is to develop the next generation of monolithic silicon pixel detectors using a 65 nm CMOS imaging process, which offers a higher logic density an…

physics.ins-det2025

The H2M Monolithic Active Pixel Sensor -- characterizing non-uniform in-pixel response in a 65 nm CMOS imaging technology

Sara Ruiz Daza, Rafael Ballabriga, Eric Buschmann +28

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensor…

physics.ins-det2024

Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process

Gianluca Aglieri Rinella, Giacomo Alocco, Matias Antonelli +91

Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise…