13 citations · 13 across the 3 of their papers we have counts for
3 papers
AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
Reusing a set of verified security assertions across RISC-V processor targets remains one of the most expensive bottlenecks in hardware security verification. Manual translation ta…
Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
RISC-V is gaining popularity for its adaptability and cost-effectiveness in processor design. With the increasing adoption of RISC-V, the importance of implementing robust security…
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini
Globalization in the semiconductor industry enables fabless design houses to reduce their costs, save time, and make use of newer technologies. However, the offshoring of Integrate…