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cs.AR2026
EstRTL: Functional Estimation Guided RTL Code Generation
Qi Xiong, Renzhi Chen, Bowei Wang +3
Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large language models (LLMs) provide new methods for the automatic generation and optimizat…
cs.AR2025
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
Zhigang Fang, Renzhi Chen, Zhijie Yang +3
Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redu…
cs.AR2025
RTLSquad: Multi-Agent Based Interpretable RTL Design
Bowei Wang, Qi Xiong, Zeqing Xiang +2
Optimizing Register-Transfer Level (RTL) code is crucial for improving hardware PPA performance. Large Language Models (LLMs) offer new approaches for automatic RTL code generation…