6 papers
TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents
Bowei Wang, Zhigang Fang, Zhijie Yang +3
Recent advances in large language models (LLMs) have led to the emergence of coding agents capable of performing complex engineering tasks, including register-transfer level (RTL)…
EstRTL: Functional Estimation Guided RTL Code Generation
Qi Xiong, Renzhi Chen, Bowei Wang +3
Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large language models (LLMs) provide new methods for the automatic generation and optimizat…
UCAgent: An End-to-End Agent for Block-Level Functional Verification
Junyue Wang, Zhicheng Yao, Yan Pi +6
Functional verification remains a critical bottleneck in modern IC development cycles, accounting for approximately 70% of total development time in many projects. However, traditi…
ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
Bowei Wang, Jiaran Gao, Yelai Feng +3
The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chi…
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
Zhigang Fang, Renzhi Chen, Zhijie Yang +3
Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redu…
RTLSquad: Multi-Agent Based Interpretable RTL Design
Bowei Wang, Qi Xiong, Zeqing Xiang +2
Optimizing Register-Transfer Level (RTL) code is crucial for improving hardware PPA performance. Large Language Models (LLMs) offer new approaches for automatic RTL code generation…