1 citations · 1 across the 5 of their papers we have counts for
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Hydra: Phase-Aware Workload Characterization of LLM Inference across Edge SoC Generations, Backends, and Quantization Levels
Amir Taherin, Sana Taghipour Anvari, Charles Amante +9
Edge LLM deployment is shaped by more than model size and precision: inference backend, hardware platform, memory traffic, and power management all affect latency and efficiency. W…
Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR
Elam Cohavi, Nicolas Bohm Agostini, Jude Haris +3
As custom hardware accelerators become increasingly central to machine learning workloads, efficient data transfer is critical for maximizing accelerator performance on linear alge…
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters,…
LLM-Driven Design Space Exploration of FPGA-based Accelerators
Vinamra Sharma, Xingjian Fu, Jude Haris +1
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompa…