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20242026
most citedData is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

59 citations · 59 across the 13 of their papers we have counts for

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Showing 2025Show all

5 papers · 1 filter

quant-ph2025

CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits

Yu Chen, Yilun Zhao, Bing Li +4

Layout Synthesis for Quantum Computing (LSQC) is a critical component of quantum design tools. Traditional LSQC studies primarily focus on optimizing for reduced circuit depth by a…

cs.AI2025

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

Zhirong Chen, Kaiyan Chang, Zhuolin Li +8

Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…

cs.AR2025

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators

Shixin Zhao, Yuming Li, Bing Li +4

Computing-in-memory (CIM) architectures demonstrate superior performance over traditional architectures. To unleash the potential of CIM accelerators, many compilation methods have…

cs.AR2025

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM

Lian Liu, Shixin Zhao, Bing Li +6

The billion-scale Large Language Models (LLMs) need deployment on expensive server-grade GPUs with large-storage HBMs and abundant computation capability. As LLM-assisted services…

cs.CR2025

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework

Kun Wang, Kaiyan Chang, Mengdi Wang +4

Recent advances of large language models in the field of Verilog generation have raised several ethical and security concerns, such as code copyright protection and dissemination o…