3 citations · 7 across the 13 of their papers we have counts for
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cs.AR2025
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Chengxi Li, Yang Sun, Lei Chen +3
This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…
cs.AR2024★ 1 cited
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Xufeng Yao, Yiwen Wang, Xing Li +6
Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization r…
cs.AR2023★ 3 cited
A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design
Zhihai Wang, Lei Chen, Jie Wang +7
Logic Synthesis (LS) plays a vital role in chip design -- a cornerstone of the semiconductor industry. A key task in LS is to transform circuits -- modeled by directed acyclic grap…