3 citations · 7 across the 13 of their papers we have counts for
13 papers
UniRTL: Unifying Code and Graph for Robust RTL Representation Learning
Yi Liu, Hongji Zhang, Lei Chen +2
Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…
SwiftMem: Fast Agentic Memory via Query-aware Indexing
Anxin Tian, Yiming Li, Xing Li +5
Agentic memory systems have become critical for enabling LLM agents to maintain long-term context and retrieve relevant information efficiently. However, existing memory frameworks…
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Chengxi Li, Yang Sun, Lei Chen +3
This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Dimitris Tsaras, Xing Li, Lei Chen +2
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Opera…
Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning
Yi Liu, Hongji Zhang, Yiwen Wang +4
Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance met…
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization
Faezeh Faez, Raika Karimi, Yingxue Zhang +4
Electronic Design Automation (EDA) is essential for IC design and has recently benefited from AI-based techniques to improve efficiency. Logic synthesis, a key EDA stage, transform…
SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation
Xinyi Zhou, Xing Li, Yingzhao Lian +6
We introduce SeaDAG, a semi-autoregressive diffusion model for conditional generation of Directed Acyclic Graphs (DAGs). Considering their inherent layer-wise structure, we simulat…
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Xufeng Yao, Yiwen Wang, Xing Li +6
Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization r…
Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers
Raika Karimi, Faezeh Faez, Yingxue Zhang +4
Contemporary hardware design benefits from the abstraction provided by high-level logic gates, streamlining the implementation of logic circuits. Logic Synthesis Optimization (LSO)…
Logic Synthesis with Generative Deep Neural Networks
Xihan Li, Xing Li, Lei Chen +3
While deep learning has achieved significant success in various domains, its application to logic circuit design has been limited due to complex constraints and strict feasibility…
SmoothGNN: Smoothing-aware GNN for Unsupervised Node Anomaly Detection
Xiangyu Dong, Xingyi Zhang, Yanni Sun +3
The smoothing issue in graph learning leads to indistinguishable node representations, posing significant challenges for graph-related tasks. However, our experiments reveal that t…
Circuit Transformer: A Transformer That Preserves Logical Equivalence
Xihan Li, Xing Li, Lei Chen +3
Implementing Boolean functions with circuits consisting of logic gates is fundamental in digital computer design. However, the implemented circuit must be exactly equivalent, which…
A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design
Zhihai Wang, Lei Chen, Jie Wang +7
Logic Synthesis (LS) plays a vital role in chip design -- a cornerstone of the semiconductor industry. A key task in LS is to transform circuits -- modeled by directed acyclic grap…