1 citations · 1 across the 3 of their papers we have counts for
3 papers
cs.AR2025
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Chengxi Li, Yang Sun, Lei Chen +3
This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…
cs.LG2025
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Dimitris Tsaras, Xing Li, Lei Chen +2
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Opera…
cs.AR2024★ 1 cited
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Xufeng Yao, Yiwen Wang, Xing Li +6
Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization r…