7 citations · 10 across the 5 of their papers we have counts for
6 papers
FlexRC: A Flexible Multi-Point Model Order Reduction Method for Many-Port RC Networks
Yuncheng Xu, Siyuan Yin, Lin Liu +4
Efficient model order reduction for many-port resistor-capacitor (RC) networks is essential in post-layout circuit simulation. Existing high-accuracy elimination-based methods have…
Bridging the Initialization Gap: A Co-Optimization Framework for Mixed-Size Global Placement
Yuhao Ren, Yiting Liu, Yanfei Zhou +4
Global placement is a critical step with high computational complexity in VLSI physical design. Modern analytical placers formulate the placement problem as a nonlinear optimizatio…
SMP-RCR: A Sparse Multipoint Moment Matching Method for RC Reduction
Siyuan Yin, Yuncheng Xu, Lin Liu +4
In post--layout circuit simulation, efficient model order reduction (MOR) for many--port resistor--capacitor (RC) circuits remains a crucial issue. The current mainstream MOR metho…
The Power of Graph Signal Processing for Chip Placement Acceleration
Yiting Liu, Hai Zhou, Jia Wang +3
Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task,…
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
Jintao Li, Haochang Zhi, Ruiyu Lyu +9
Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluati…
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Hongyang Pan, Cunqing Lan, Yiting Liu +5
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages…