17 citations · 26 across the 4 of their papers we have counts for
4 papers
EPAC: The Last Dance
Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino +36
This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European…
RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin
Pablo Vizcaino, Filippo Mantovani, Jesus Labarta +1
Simulators are crucial during the development of a chip, like the RISC-V accelerator designed in the European Processor Initiative project. In this paper, we showcase the limitatio…
Short reasons for long vectors in HPC CPUs: a study based on RISC-V
Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou +3
For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-Performance Computing (HPC) and mobile technology. Typical commercially-available SIMD units proc…
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study
Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli +6
Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., compiler…