10 citations · 24 across the 14 of their papers we have counts for
8 papers · 1 filter
FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
Deepak Narayan Gadde, Aman Kumar, Djones Lettnin +1
Ever-increasing design complexity of System-on-Chips (SoCs) led to significant verification challenges. Unlike software, bugs in hardware design are vigorous and eternal i.e., once…
Analogous Alignments: Digital "Formally" meets Analog
Hansa Mohanty, Deepak Narayan Gadde
The complexity of modern-day System-on-Chips (SoCs) is continually increasing, and it becomes increasingly challenging to deliver dependable and credible chips in a short time-to-m…
Generative AI Augmented Induction-based Formal Verification
Aman Kumar, Deepak Narayan Gadde
Generative Artificial Intelligence (GenAI) has demonstrated its capabilities in the present world that reduce human effort significantly. It utilizes deep learning techniques to cr…
Towards Efficient Design Verification -- Constrained Random Verification using PyUVM
Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar
Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based…
Effective Design Verification -- Constrained Random with Python and Cocotb
Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar
Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verificat…
Efficient Stimuli Generation using Reinforcement Learning in Design Verification
Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar +3
The increasing design complexity of System-on-Chips (SoCs) has led to significant verification challenges, particularly in meeting coverage targets within a timely manner. At prese…
Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification
Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin +1
The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and runni…
All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
Deepak Narayan Gadde, Aman Kumar, Thomas Nalapat +2
Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the form…