10 citations · 24 across the 14 of their papers we have counts for
15 papers
Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification
Vaisakh Naduvodi Viswambharan, Keerthan Kopparam Radhakrishna, Deepak Narayan Gadde +1
Recent advances in Large Language Models (LLMs) have enabled workflows that generate SystemVerilog Assertions (SVAs) from natural-language specifications, with the potential to acc…
Agentic AI-based Coverage Closure for Formal Verification
Sivaram Pothireddypalli, Ashish Raman, Deepak Narayan Gadde +1
Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fa…
Saarthi for AGI: Towards Domain-Specific General Intelligence for Formal Verification
Aman Kumar, Deepak Narayan Gadde, Luu Danh Minh +3
Saarthi is an agentic AI framework that uses multi-agent collaboration to perform end-to-end formal verification. Even though the framework provides a complete flow from specificat…
Formal that "Floats" High: Formal Verification of Floating Point Arithmetic
Hansa Mohanty, Vaisakh Naduvodi Viswambharan, Deepak Narayan Gadde
Formal verification of floating-point arithmetic remains challenging due to non-linear arithmetic behavior and the tight coupling between control and datapath logic. Existing appro…
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Vaisakh Naduvodi Viswambharan +4
Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach…
Saarthi: The First AI Formal Verification Engineer
Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna +1
Recently, Devin has made a significant buzz in the Artificial Intelligence (AI) community as the world's first fully autonomous AI software engineer, capable of independently devel…
Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach
Suruchi Kumari, Deepak Narayan Gadde, Aman Kumar
The escalating complexity of System-on-Chip (SoC) designs has created a bottleneck in verification, with traditional techniques struggling to achieve complete coverage. Existing te…
FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
Deepak Narayan Gadde, Aman Kumar, Djones Lettnin +1
Ever-increasing design complexity of System-on-Chips (SoCs) led to significant verification challenges. Unlike software, bugs in hardware design are vigorous and eternal i.e., once…
Analogous Alignments: Digital "Formally" meets Analog
Hansa Mohanty, Deepak Narayan Gadde
The complexity of modern-day System-on-Chips (SoCs) is continually increasing, and it becomes increasingly challenging to deliver dependable and credible chips in a short time-to-m…
Generative AI Augmented Induction-based Formal Verification
Aman Kumar, Deepak Narayan Gadde
Generative Artificial Intelligence (GenAI) has demonstrated its capabilities in the present world that reduce human effort significantly. It utilizes deep learning techniques to cr…
Towards Efficient Design Verification -- Constrained Random Verification using PyUVM
Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar
Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based…
Effective Design Verification -- Constrained Random with Python and Cocotb
Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar
Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verificat…
Efficient Stimuli Generation using Reinforcement Learning in Design Verification
Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar +3
The increasing design complexity of System-on-Chips (SoCs) has led to significant verification challenges, particularly in meeting coverage targets within a timely manner. At prese…
Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification
Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin +1
The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and runni…
All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
Deepak Narayan Gadde, Aman Kumar, Thomas Nalapat +2
Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the form…