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cs.LG2024
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…
cs.LG2024
HardCore Generation: Generating Hard UNSAT Problems for Data Augmentation
Joseph Cotnareanu, Zhanguang Zhang, Hui-Ling Zhen +2
Efficiently determining the satisfiability of a boolean equation -- known as the SAT problem for brevity -- is crucial in various industrial problems. Recently, the advent of deep…